# Booth’s multiplier – Yet another :)
Uncategorized @ 25 November 2012
Hi,
Last week in my qualification examination booth’s multiplier, data processing unit and ASM chart was asked as a basic computer organization question. Now I try to write the multiplier in VHDL as a state-by-state calculation for basic computer. Any comments are welcome.
My syntax highlighter is a little weird though any help is appreciated 🙂 You know these software stuff is for the coders, not for the hardware guys. Sorry for the inconvenience. Copy paste the code to your favorite text editor. Booth multiplier VHDL code for basic computer organization.
Please download from here.
--------------------------------------------------------------------
-- Company : -
-- Engineer : Enes Erdin
-- Creation Date : 25.11.2012
-- Copyright : 2012 Enes Erdin
--
-- Description:
-- This is a booth multiplier written for basic computer organization
--
-- Warning : This code is as-is. The author of the code is not responsible
-- for any damage on your system
--
-- License:
-- This code can be freely distributed and modified as long as
-- this header is not removed.
--
-- contact : contact me via gmail.com
--------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity booth_mul is
end entity booth_mul;
architecture sinav of booth_mul is
signal clk : std_logic := '0';
signal BR : unsigned(5 downto 0) := "000000";
signal QR : unsigned(6 downto 0) := "0000000";
signal SC : unsigned(5 downto 0) := "000000";
signal AC : unsigned(5 downto 0) := "000000";
signal RESULT : unsigned(11 downto 0) := (others => '0');
signal CS_INTEGER : integer := 0;
type state_type is (T0,T1,T2,T3,T4,T5,T7,T6);
signal cs : state_type;
begin
clk <= not clk after 5 ns;
CS_INTEGER <= 0 when cs = T0 else
10 when cs = T1 else
20 when cs = T2 else
30 when cs = T3 else
40 when cs = T4 else
50 when cs = T5 else
60 when cs = T6 else
70 when cs = T7 else
9999;
process(clk)
procedure ashr_AC_QR is
begin
QR <= AC(AC'low) & QR(QR'high downto QR'low+1);
AC <= AC(AC'high) & AC(AC'high downto AC'low+1);
end procedure;
begin
if rising_edge(clk) then
case cs is
when T0 =>
cs <= T1;
QR <= "1001010";-- -27 -- last bit represents Qn+1
SC <= "000110"; -- 6 eder
BR <= "011010"; -- 26
when T1 =>
--BR <= BR_orig;
case QR(1 downto 0) is
when "00" | "11" =>
cs <= T7;
when "01" => -- ADD
cs <= T2;
when "10" => -- subtract
cs <= T3;
when others =>
NULL;
end case;
when T2 =>
AC <= AC+BR;
cs <= T7;
when T3 =>
BR <= not BR;
cs <= T4;
when T4 =>
AC <= AC+BR+1; -- a full adder with Cin = 1;
BR <= not BR; -- and convert to the original
cs <= T7;
when T7 =>
ashr_AC_QR;
SC <= SC-1;
cs <= T5;
when T5 =>
if SC = "000000" then
cs <= T6;
else
--cs <= T1; -- lower the required clock cycle
case QR(1 downto 0) is
when "00" | "11" =>
cs <= T7;
when "01" => --ADD
cs <= T2;
when "10" => -- subtract
cs <= T3;
when others =>
NULL;
end case;
end if;
when T6 =>
result <= AC & QR(QR'high downto QR'low+1);
cs <= T6;
when others =>
NULL;
end case;
end if;
end process;
end;
GHDL compilation and simulation code :
ghdl -a booth_mul.vhd ghdl -e booth_mul ghdl -r booth_mul --stop-time=500ns --vcd=booth_mul.vcd gtkwave booth_mul.vcd |